FPGA Design & Programming and Comparison to ASIC

A schematic design or a hardware description language (HDL) is provided by the user to define the behavior of the FPGA. The HDL form should be used to work with huge structures because it is feasible to exactly specify them by numbers rather than having to draw every piece manually. On the other hand, simpler visualization of a design is the main advantage of schematic entry.

Then, utilizing an electronic design automation tool, a technology-mapped netlist is created. The netlist can then be fitted to the real FPGA architecture using a method called place-and-route, usually executed by the FPGA Company’s proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is done, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is shifted to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device.

VHDL and Verilog are the most common HDLs, though in order to minimize the complexity of designing in HDLs, which are in comparison to the equiponderant to the assembly languages, there are steps to increase the abstractiveness level through the introduction of substitute languages. For targeting and programming FPGA hardware, an FPGA add-in module is available to National Instruments' LabVIEW graphical programming language (sometimes referred to as "G").

Formerly, FPGAs (Field programmable Gate Array) lagged behind than their rigid ASIC (Application-specific integrated circuit) peers in terms of operational speed, energy efficiency and overall functionality. It was demonstrated by an older research that designs executed on FPGAs require on an average 40 times as much area, pull 12 times as much dynamic power, and achieve one third the speed of resembling ASIC executions. In the modern days, FPGAs like Virtex-7 from Xilinx or Stratix 5 from Altera have taken place to contend with resembling ASIC and ASSP solutions by providing notably minimized power, extended speed, and decreased cost of materials, least execution real-estate and expanded likelihood for re-configuration 'on-the-fly'. A design can now be attained using just one FPGA where 6-10 ASIC may have been used in the same design in the past.

Conveniences of FPGAs comprise the facility to reprogram in the area to fix bugs, and can comprise a briefer time for marketing and lesser non-recurring engineering expenses. A moderate road can be taken by the vendors by developing their hardware on common FPGAs, but manufacture their ultimate version as an ASIC. As a result of this, it cannot be modified any longer after the design has been implemented.

Specified uses of FPGAs comprise ASIC prototyping, digital signal processing, computer hardware emulation, software-defined radio, medical imaging, bioinformatics, computer vision, speech identification, cryptography, metal detection, radio astronomy and an increasing extent of other areas.

In the beginning, FPGAs started as challengers to CPLDs and contended in an analogous space, that of glue logic for PCBs. As their size, capacity, and speed enhanced, they started to takeover bigger and bigger functions to the point where few are now marketed as complete systems on chips (SoC). Especially with the launch of dedicated multipliers into FPGA architectures in the late 1990s, applications which had conventionally been the only reserve of DSPs started to incorporate FPGAs instead.

One more tendency on the usage of FPGAs is hardware acceleration, where one can use the FPGA to accelerate particular parts of an algorithm and share part of the computation between the FPGA and a general processor.