FPGA Design & Programming

A schematic design or a hardware description language (HDL) is provided by the user to define the behavior of the FPGA. The HDL form should be used to work with huge structures because it is feasible to exactly specify them by numbers rather than having to draw every piece manually. On the other hand, simpler visualization of a design is the main advantage of schematic entry.

Then, utilizing an electronic design automation tool, a technology-mapped netlist is created. The netlist can then be fitted to the real FPGA architecture using a method called place-and-route, usually executed by the FPGA Company’s proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is done, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is shifted to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device.

VHDL and Verilog are the most common HDLs, though in order to minimize the complexity of designing in HDLs, which are in comparison to the equiponderant to the assembly languages, there are steps to increase the abstractiveness level through the introduction of substitute languages. For targeting and programming FPGA hardware, an FPGA add-in module is available to National Instruments' LabVIEW graphical programming language (sometimes referred to as "G").

Dual in-Line Package for Integrated Circuits

Dual in-line package (known as DIP or DIL) is one of the most common among many kinds of IC packages with distinguishable measures, mounting styles, and/or pin-enumerations. In terms of microelectronics, a package of electronic components which has two parallel lines of electrical connecting pins and cased in a rectangular housing is known as dual in-line package. It can be either inserted in a socket or through-hole ascended to a printed circuit board. In 1964, Don Forbes, Bryant Rogers and Rex Rice invented the dual-inline ordination at Fairchild Research & Development. It was during that period, when the limited number of leads obtainable on circular transistor-style packages became a restriction in the application of integrated circuits. Additional signal and power supply leads are needed by the more and more complex circuits (according to the Rent’s rule); in the end, microprocessors and analogous complicated devices needed leads to a greater extent than could be put on a DIP package, which leads to the development of highly dense packages. Moreover, rectangular & square packages made it effortless to route printed-circuit traces underneath the packages.

A DIP is generally mentioned as a DIPn, where n is the aggregate number of pins. We can say for example, a DIP14 microcircuit package would consist of two rows of seven vertical leads. Most common DIP packages have four (lowest) to 64 (at most). Numerous digital and analog IC types are attainable in DIP package forms.

FPGA and it’s Technical Design

Contemporaneous field-programmable gate arrays (FPGAs) have huge provision of logic gates and RAM blocks to execute complicated digital calculations. It is a challenge to verify right timing of valid data within setup time and hold time because FPGA designs employ very fast I/Os and bidirectional data buses. For meeting these time constraints, floor planning enables resources allocation. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

Some FPGAs have analog features in addition to digital functions. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slowly. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

Xilinx and Field Programmable Gate Arrays

Semiconductor Devices which are founded around a matrix of configurable logic blocks (CLBs) and linked through programmable interconnects known as Field Programmable GateArrays (FPGAs). These semiconductors can be reprogrammed for the intended applications and operational necessities after manufacture. Because of this distinctive feature, FPGAs are different from Application Specific Integrated Circuits (ASICs). ASICs are custom made for particular applications. Though one-time programmable (OTP) FPGAs are there, most types are based on SRAM which can be reprogrammed as the design advances.

ASIC and FPGAs have various value propositions, and they require to be carefully assessed before choosing any one over the other. Information is easily available about comparison between these two technologies. Today’s FPGAs thrust the 500MHz performance hurdle without any problem, though FPGAs used to be chosen for lower volume/speed/complexity design traditionally. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price points, FPGAs are an enthralling choice for nearly any type of design.

FPGAs are perfectly suitable for various markets. Being the pioneer in the industry, Xilinx offers extensive solutions comprising FPGA devices, advanced software, and configurable, ready-to-use IP cores for markets and applications such as: Aerospace & Defense, ASIC Prototyping, Audio, Automotive, Broadcast, Consumer Electronics, Data Center, High Performance Computing and Data Storage, Industrial, Medical, Security, Video and image processing, wired communication and wireless communication.

SiC & GaN Power Semiconductors Market to Get Bigger 17-fold to $2.5 Billion Within 2023

Powered by increasing need for hybrid and electric vehicles, power supplies, photovoltaic (PV) inverters and various conventional applications, the rising worldwide market for gallium nitride power semiconductors and silicon carbide will get bigger by an aspect of 17 over the 10 years from 2013 (only $150 million) to 2023 ($2.5 billion), forecasts market research firm IHS Inc in the report 'The World Market for SiC & GaN Power Semiconductors - 2014 Edition.

SiC and GaN power semiconductors have been attempting to vindicate themselves in main applications for a several years now. Nevertheless, around 15% of the end market could comprise of latest applications utilizing these device technologies those are presently still two or three years away from production. Alongside with the market for hybrid and electric vehicles themselves, at present it is obvious that the market for electric vehicle charging infrastructure together with battery charging stations for plug-in hybrid and battery-electric vehicles - is also a possible attractive field for SiC and GaN power devices.

No unanimous universal standard is there for hybrid-electric vehicle (HEV) charging infrastructure, so there are different contending standards narrating the diverse modes or levels for AC and DC charging. Each of the miscellaneous AC levels can be taken into account for electro-mechanical system, which needs few, if any, power semiconductors. The IHS report hence only takes in account 'fast charging' or DC systems as these are AC-DC power supplies, transmuting power from the mains (generally three-phase) into very high currents of up to 125-400A at direct-current voltages up to 480-600VDC (distributing a highest power of 240kW).

Wireless power charges battery-operated apparatuses by emitting power via air instead of via power cables. Even though nearness within a stated limit is necessary, this new technology is acquiring popularity in cell phones, notebook computers, game controllers, tablets, electric vehicles, and other consumer products. The reception of SiC and GaN power semiconductors will be unimportant in inductive charging solutions, which are intended to consent with the Wireless Power Consortium (WPC) Qi or Power Matters Alliance (PMA) standards whereas silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) are sufficient for the low frequencies engaged. In contradiction, the rapid-switching abilities of SiC and GaN power semiconductors are perfect for magnetic-resonance power-transfer applications, which execute nicely at the higher frequencies of the Alliance for Wireless Power (A4WP) standard.

There are two other applications which could possibly utilize SiC power modules. These are traction and wind turbines. Their high cost, unverified reliableness, and a shortage of availableness of high-current-rated modules are the biggest obstacles to adoption in both instances, in general, and of full SiC modules particularly. Both applications typically need 1700V modules, a voltage at which small numbers of SiC transistors have already been developed. Samples are on their way of production, but profit-oriented manufacture is not prospective to begin until 2016 or 2017.

For high-powered SiC technologies, there are numerous newly developed medical applications and other possible industrial applications. For low-voltage GaN devices, the latest applications comprise numerous rising technologies those are awaited to drive important development in the future, such as light detection, wireless envelope tracking, and ranging (LIDAR), medical devices and  Class-B audio amplifiers.

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Demonstration of Wafer-Scale Graphene Integrated Circuit Smaller Than a Pinhead For Wireless Devices

It is alleged by the scientists of IBM research that they have reached a milestone in forming a building block for the subsequent wireless devices. In a paper disclosed in the journal Science, IBM researchist made public the maiden integrated circuit built from wafer-size graphene, and revealed a broadband frequency mixer functioning at frequencies up to 10 gigahertz (10 billion cycles per second).

Aimed at wireless communications, this analog integrated circuit based on graphene would make better recent wireless devices and beckons to the possibility for a new set of applications. Among the conventional frequencies of present, transceiver and cell phone signals could be advanced, possibly allowing phones to function where they can't today while, at much higher frequencies, military and medical personnel could see covert weapons or operate medical imaging without the similar radiation riskiness of X-rays.

Graphene is the narrowest electronic material which is composed of a single layer of carbon atoms packed in a honeycomb formation, possesses exceptional electrical, mechanical, optical and thermal characteristics that could make it not so much costly and use less power in mobile electronics like smart phones.

In spite of noteworthy scientific advancement in the comprehension of this unprecedented material and the demonstration of high-performance graphene-based devices, the difficulty of combining graphene transistors with other components on an individual chip had not been cognized up to now, majorly because of the deficient adherence of graphene with metals and oxides and the need of dependable fabrication schemes to generate formative circuits and devices.

This latest integrated circuit is composed of a graphene transistor and a set of two inductors compactly built-in on a silicon carbide (SiC) wafer, surpasses these design obstacles by advancing wafer-scale fabrication methods that keep up the standard of graphene and, at the same time, make allowance for its consolidation to other elements in an intricate circuitry.

In this presentation, thermal annealing of SiC wafers synthesized graphene to comprise stable graphene layers on the surface of SiC. Four layers of metal and two layers of oxide are needed by the fabrication of graphene circuits to make top-gated graphene transistor, interconnects and on-chip inductors.

The circuit functions as a broadband frequency mixer, which generates output signals with varied frequencies (aggregate and difference) of the input signals. Mixers are considered as basic elements of various electronic communication systems. This graphene integrated circuit has been presented as capable of frequency mixing up to 10 GHz and fantastic thermal stability up to 125°C

The fabrication scheme demonstrated can also be used in other types of graphene materials, including chemical vapor deposited (CVD) graphene films synthesized on metal films, and are also suitable for optical lithography for minimized cost and throughput. In the past, the team has demonstrated stand-alone graphene transistors with a cut-off frequency as high as 100 GHz and 155 GHz for epitaxial and CVD graphene, for a gate length of 240 and 40 nm, respectively.

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FPGA Comparison

Formerly, FPGAs (Field-programmable Gate Array) lagged behind than their rigid ASIC (Application-specific integrated circuit) peers in terms of operational speed, energy efficiency and overall functionality. It was demonstrated by an older research that designs executed on FPGAs require on an average 40 times as much area, pull 12 times as much dynamic power, and achieve one third the speed of resembling ASIC executions. In the modern days, FPGAs like Virtex-7 from Xilinx or Stratix 5 from Altera have taken place to contend with resembling ASIC and ASSP solutions by providing notably minimized power, extended speed, and decreased cost of materials, least execution real-estate and expanded likelihood for re-configuration 'on-the-fly'. A design can now be attained using just one FPGA where 6-10 ASIC may have been used in the same design in the past.

Conveniences of FPGAs comprise the facility to reprogram in the area to fix bugs, and can comprise a briefer time for marketing and lesser non-recurring engineering expenses. A moderate road can be taken by the vendors by developing their hardware on common FPGAs, but manufacture their ultimate version as an ASIC. As a result of this, it cannot be modified any longer after the design has been implemented.