Contemporaneous field-programmable gate arrays (FPGAs) have huge provision of logic gates and RAM blocks to execute complicated
digital calculations. It is a challenge to verify right timing of valid data
within setup time and hold time because FPGA designs employ very fast I/Os and
bidirectional data buses. For meeting these time constraints, floor planning
enables resources allocation. FPGAs can be used to implement any logical
function that an ASIC could perform. The ability to update the functionality
after shipping, partial re-configuration of a portion of the design and the low
non-recurring engineering costs relative to an ASIC design (notwithstanding the
generally higher unit cost), offer advantages for many applications.
Some FPGAs have analog features in addition
to digital functions. The most common analog feature is programmable slew rate
and drive strength on each output pin, allowing the engineer to set slow rates
on lightly loaded pins that would otherwise ring or couple unacceptably, and to
set stronger, faster rates on heavily loaded pins on high-speed channels that
would otherwise run too slowly. Another relatively common analog feature is
differential comparators on input pins designed to be connected to differential
signaling channels. A few "mixed signal FPGAs" have integrated
peripheral analog-to-digital converters (ADCs) and digital-to-analog converters
(DACs) with analog signal conditioning blocks allowing them to operate as a
system-on-a-chip. Such devices blur the line between an FPGA, which carries
digital ones and zeros on its internal programmable interconnect fabric, and
field-programmable analog array (FPAA), which carries analog values on its internal
programmable interconnect fabric.
