Different Behaviors of Paralleling IGBTS Published

The paralleling behavior for IGBTs deserves of an special attention that has to be given to the drive circuit, this is due to the variation of the gate threshold voltage of the different chips, simply connecting the gates is not adequate. As they are not just a few of them but several, Instead, each gate has to be driven by its own gate resistor in order to ensure that the chip with the lowest threshold voltage does not clamp the voltage for the others and carry all the current.

The layout of the emitter circuit has to be very symmetrical in order to minimize differences in emitter inductances and resistances. Even minor, unavoidable differences in the emitter inductances and resistances will generate compensation currents between the gate drive emitter connections. It is recommended to use a resistor in the range of at least 0.5 Ohm, but not to exceed approximately 1/3 of the total gate resistance.

The on-state behavior is something more critical when it comes about paralleling igbts. Some devices such as the P700 six-pack suggests a relatively variation in IGBT collector-emitter and diode forward voltage. For the IGBT, the collector-emitter saturation voltage at 25 °C is given as 1.7 V typical and 2.25 V maximum. No value is provided for the minimum voltage. Keeping this in mind, the paralleling of chips cannot be recommended, since the current sharing among the individual IGBTs cannot be ensured. The situation is even worse for the diodes in parallel systems but it can be avoided depending it its final use.

However based in the present times, the actual spread of the devices within one power module is lower than the parallel system users. This is due to the fact that they are picked from locations either exactly next or very close to each other on the same wafer, and will as is stated, feature similar electrical characteristics. Using multiple smaller chips instead of one larger chip improves the thermal behavior, as they doesn`t heat as quickly as a larger one, they tend to devides the heating properties well, This is due to the fact that not only the chip itself, but also a certain area around the chip, will participate in the transfer of heat from the chip to the heatsink. Parallelling systems have improved thermal spreading when using two small chips instead of one large, with in equal total area in both cases.

This case can also be seen when comparing the thermal resistance of the 100 A IGBT in the P569-F module with the 35 A IGBT in the P700-F module. The thermal resistance junction to heatsink for the 100 A the device is 0,57 K/W. The resistance for the single 35 A IGBT is 1,29 K/W, resulting in an resistance of 0,43 K/W, when 3 of them are used in parallel. This provides an improvement of about 25 % in thermal performance,one point for these kind of system, that left behind the more traditional one-module igbt old system,this also compensates for some if not all of the de-rating required due to the non-ideal current sharing.