FPGA Design & Programming

A schematic design or a hardware description language (HDL) is provided by the user to define the behavior of the FPGA. The HDL form should be used to work with huge structures because it is feasible to exactly specify them by numbers rather than having to draw every piece manually. On the other hand, simpler visualization of a design is the main advantage of schematic entry.

Then, utilizing an electronic design automation tool, a technology-mapped netlist is created. The netlist can then be fitted to the real FPGA architecture using a method called place-and-route, usually executed by the FPGA Company’s proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is done, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is shifted to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device.

VHDL and Verilog are the most common HDLs, though in order to minimize the complexity of designing in HDLs, which are in comparison to the equiponderant to the assembly languages, there are steps to increase the abstractiveness level through the introduction of substitute languages. For targeting and programming FPGA hardware, an FPGA add-in module is available to National Instruments' LabVIEW graphical programming language (sometimes referred to as "G").